In the present day, three dimensional transistor (3D) devices are used to provide increased performance over planar transistors. Devices such as finFET devices and horizontal-Gate-All-Around (HGAA) FETs are formed from fin-shaped semiconductor regions extending perpendicularly from a substrate plane, such as the plane of a silicon wafer. A narrow structure made of silicon or other semiconductor material may be formed within an HGAA FET or similar device structure, where the narrow structure is elongated in a first direction that defines the direction of current flow in the device structure. The narrow structure may have a cross section in the narrow direction(s) whose dimensions are on the order of 50 nm or less, in some examples, less than 10 nm. Such structures may be integrated within a gate of the device to be formed so as to define a channel. In the case of silicon, such narrow structures may be referred to as silicon nanowires. Such nanowires may be horizontal or parallel to the surface or vertical or orthogonal to the surface of the wafer.
In some approaches of HGAA devices (“the term “HGAA device” is used interchangeably with “HGAA FET device”), the silicon nanowires are formed by fabricating a multilayer structure comprising alternating layers of silicon and silicon:germanium alloy (SiGe) within a fin structure. The overall geometry of the HGAA device after fin formation may resemble a conventional finFET formed of just silicon. Layers of SiGe adjacent a given silicon layer within the fin structure may be selectively removed in an exposed region of the fin structure, allowing the silicon layer within the former fin structure to be exposed on all sides, thus forming a free standing portion of a nanowire in a channel region of the device to be formed. This facilitates formation of gate material on all sides of the exposed free standing nanowire.
While HGAA FET structures afford the ability to electrically gate a silicon nanowire on all sides, the formation of HGAA devices according to known approaches is complicated. Device fabrication may be limited by masking and etch processes, where the width a fin cannot be well controlled below 10 nm. Additionally using known approaches, a superlattice made of silicon and SiGe may have an upper limit in germanium concentration in the SiGe layer of 30% due to lattice mismatch and defect generation when germanium concentration increases. Additionally, the known approaches for HGAA formation using Si/SiGe superlattices has limited ability to strain the resultant silicon nanowire coaxially.
There remains a need for nanostructures and methods of making nanostructures that overcome the aforementioned deficiencies.